1. Field of the Invention
This invention relates to computer systems and more specifically to a clock division chip for interfacing a microprocessor to support circuitry.
2. Description of the Prior Art
The frequency at which microprocessors operate within computer systems has progressively increased with advances in microprocessor design and technology. Required execution time for performing specific microprocessor operations has consequently decreased, thus improving the efficiency of the computer system.
Design of microprocessors capable of operating at higher execution frequencies has been an ongoing developmental objective. However, with silicon-based microprocessors approaching theoretical limits in density of features and therefore circuit speed, designers are exploring new materials, such as galium arsenide, to develop microprocessors which operate at higher frequencies.
The speed at which a computer system accomplishes a particular task is usually not, however, exclusively dependent simply upon the speed of the microprocessor. The speed of support circuitry and system memory can also dictate the time required to perform a particular task. It is desirable to provide data to and from the main memory, peripherals, and microprocessor without limiting the speed at which the program code is processed. Unfortunately, much of the system memory and peripherals are incapable of handling data at the speed of the microprocessor. This incapability degrades the overall performance of the system.
Since the main memory is often slower than the microprocessor, wait states are required when the memory is being accessed. The required wait states cause corresponding delays in the speed of the overall computer system.
To improve system speed, a faster cache memory system is commonly used. A cache memory is interposed in the memory hierarchy between main memory and the CPU (central processing unit) to improve effective memory transfer rates and, accordingly, raise processing speeds. The name "cache memory" refers to the fact that the memory is essentially hidden and appears transparent to the user, who is aware only of an apparently higher-speed large main memory. The cache memory is usually implemented by semiconductor devices whose speeds are compatible with that of the processor, while the main memory utilizes a less costly, lower-speed semiconductor technology. The cached concept anticipates the likely reuse by the CPU of information in main storage by organizing a copy of the information in cache memory. Often, for example, approximately 90% of the software code being executed resides in the cache memory.
Support interface circuitry for the computer system typically includes a CPU/Memory controller, a peripheral controller, and a bus bridge interface. As microprocessors are upgraded to operate at higher frequencies, it is often necessary to upgrade and redesign the support interface circuitry to allow for operation at the higher frequencies. The cost of upgrading the design of the support interface circuitry is often high, however. Manufacturing costs are correspondingly high since semiconductor production processes must be modified to produce the upgraded faster operating circuitry.
The GCK131 80386 AT Compatible Three Chip Set, sold by G-2 Incorporated, is an example of a set of support interface circuitry. The GCK131 Chip Set consists of three highly integrated HCMOS microchips and supports an Intel 80386 microprocessor based computer system in AT-compatible mode at speeds up to 25 MHZ. The three chip set allows the implementation of a computer system with simply an 80386 microprocessor, a keyboard controller, a real time clock, several semiconductor devices, and memory.
The GCK131 Chip Set includes the GC131 Peripheral Controller, the GC132 CPU/Memory Controller, and the GC133 Bus Bridge Interface. A block diagram of a typical 80386 system using the GCK131 Chip Set is shown in FIG. 1. The GC131 Peripheral Controller supports the system with conventional INTERRUPT, TIMER, DMA/REFRESH, and I/O services. The GC132 CPU/Memory Controller controls the CPU and the memory including control of timing, synchronization, addressing, parity, bus conversion, and the AT bus module. The GC133 transfers data between the high-speed bus to the slower ATD bus. The GC133 Bus Bridge Interface essentially consists of a buffer, latch, and comparator.
The GCK131 Chip Set is designed to operate at a maximum frequency of 25 MHZ. Until recently, the Intel 80386 microprocessor also had a maximum operating frequency of 25 MHZ. In response to demand for faster microprocessors, however, Intel developed an 80386 microprocessor which operates at 33 MHZ. The GCK131 Chip Set is unable to operate at frequencies above 25 MHZ. It would be a difficult and expensive developmental task to upgrade the allowable operating frequency of the GCK131 Chip Set to 33 MHZ.